/*
 * wdt_operate.h - CSP define of LomboTech SPI Controller
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include <linux/types.h>
#include <mach/csp.h>

/* register offset define */
#define LOMBO_WDOG_RL              (0x08)  /* clock control register */
#define LOMBO_WDOG_CTRL            (0x10)  /* control register */
#define LOMBO_WDOG_STORE           (0x14)  /* store value register */
#define LOMBO_WDOG_CUR_VAL         (0x18)  /* counter current value register */
#define LOMBO_WDOG_RESTART         (0x1C)  /* restart register */
#define LOMBO_WDOG_INT_EN          (0x20)  /* interrupt enable register */
#define LOMBO_WDOG_CLR_INT_PENDING (0x24)  /* clear int pending register */
#define LOMBO_WDOG_INT_PENDING     (0x28)  /* interrupt pending register */

#define LOMBO_WATCHDOG_DEFAULT_TIME	(16 * 1000)		/* 16s */
#define LOMBO_WATCHDOG_MAX_TIMEOUT	(524 * 1000)		/* 524s */
#define LOMBO_WATCHDOG_MIN_TIMEOUT	(1)			/* 1ms */

/* clock control */
#define LOMBO_WDOG_CLK_SRC_RTCCLK \
	(WDOG_WDOG_CTRL_SEL_1)
#define LOMBO_WDOG_CLK_SRC_32K_HARDCODED_DIVIDED_BY_HFEOSC \
	(WDOG_WDOG_CTRL_SEL_0)

/* response mode */
#define LOMBO_WDOG_FIRST_INTERRUPT_THEN_RESET_RESP_MOD \
	(WDOG_WDOG_CTRL_RMOD_0)
#define LOMBO_WDOG_INTERRUPT_RESP_MOD \
	(WDOG_WDOG_CTRL_RMOD_1)

/* calculate store value for LOMBO_WDOG_STORE.STORE */
#define MSEC_TO_STORE(msec)	(msec << 5)
#define STORE_TO_MSEC(value)	(value >> 5)

extern void csp_wdt_unlock_reg(void *base);
extern void csp_wdt_lock_reg(void *base);
extern void csp_wdt_clr_int_pend(void *base);
extern u32 csp_wdt_get_int_pend(void *base);
extern void csp_wdt_int_enable(void *base, u32 value);
extern void csp_wdt_set_store(void *base, u32 value);
extern void csp_wdt_restart_store(void *base, u32 value);
extern void csp_wdt_set_response_mod(void *base, u32 value);
extern void csp_wdt_clk(void *base, u32 value);
extern u32 csp_wdt_get_status(void *base);
extern int csp_wdt_enable(void *base);
extern int csp_wdt_disable(void *base);
extern void csp_wdt_restart(void *base);
extern void csp_wdt_init_register(void *base);
extern u32 csp_wdt_get_current(void *base);

extern void csp_wdt_set_timeout(void *base, u32 value);
extern void csp_wdt_get_timeleft(void *base, u32 *value);
extern void csp_wdt_set_reboot_time(void *base);
